This invention relates to increasing the efficiency with which signals from area array packages (BGAs and CGAs) are extracted and routed on the printed circuit boards (PCB or circuit card) on which these devices are mounted.
It is well established that the increase in area array connections (pin count) translates to an increase in the number of printed circuit board routing layers needed to support the device escape and routing circuits. The incentive for further increases in routing efficiency stem from the cost and complications related to the added layers needed to for typical routing methodologies.
At one extreme, where the area array pin count may be relatively low, implementation of higher efficiency routing methodologies are driven solely by the cost savings associated with the resulting lower layer count PCB.
As pin count increases above 1000 pins, limitations in high layer count PCB fabrication capabilities, shift the incentive towards minimizing the overall layer count, thereby improving the quality and reliability of a PCB for a given design, while also allowing the design to benefit from cost savings.
Finally, at the other extreme, area array technology is following a design trend towards higher pin counts (>2500) and finer pitches (<0.8 mm) which may not be usable at all, without improved routing solutions like the one disclosed herein.
The prior art has used shared through-vias on power and ground connections aligned in columns in order to form a routing channel (i.e. a larger space between the row of shared vias and an adjacent row) through which connections can be routed. (See FIG. 1).
The prior art solution places additional constraints on the pinout configuration of the area array device power and ground pins, which require a high degree of adherence to a specific pinout pattern which in the extreme may not be achievable by certain area array packaging styles. In general these added constraints are undesirable from a signal integrity standpoint. Furthermore, that solution involves the sharing of adjacent power and ground pins which is also an unfavorable practice due to the negative impact that it might have on device functionality.